Flip-flops have a wide variety of uses in today's computers and digital circuits. A flip-flop is used to generate a steady state output signal having either a high (logical one) or a low (logical zero) potential. As the uses for flip-flops increase, the desire to improve flip-flop performance and the desire to reduce power consumption has led to increased demand for high performance low power consumption flip-flops. Flip-flops are one of the most commonly used elements to implement sequential circuits, that is circuits in which the primary output relies not only on the current values of the input, but also the previous input values.
A prior art flip-flop 100 is shown in FIG. 1 and comprises p-type transistor 102 and n-type transistors 104, 106, and 108 connected in series between a high potential 110 and ground potential 112, p-type transistor 114 and n-type transistors 116, 118, and 120 connected in series between a high potential 110 and ground potential 112, three inverters 122, p-type transistors 124 and 126, and latch 128. Inverters 122 are coupled in series between clock signal CK and the gate of transistor 108. Clock signal CK is also connected to the gates of transistors 102, 104, and 116. The complement of clock signal CK, signal CK*, is connected to the gates of transistors 120 and 126. A data input D is connected to the gates of transistors 106 and 124. A node 130 is defined at the connection between transistors 102 and 104. Node 130 is also connected to the gates of transistors 114 and 118. Transistors 124 and 126 are connected between high potential 110 and node 130. Latch 128 is connected to node 132 which is between transistors 114 and 116.
The operation of flip-flop 100 is straightforward. In flip-flop 100, when CK is low, node 130 is precharged to high voltage 110, and transistors 108 and 120 are on, while transistors 104 and 116 are off. Node 132 holds its previous value. On the rising edge of clock CK, transistor 102 turns off and transistors 104 and 116 turn on. Transistors 108 and 120 remain on for the delay period of inverters 122. Data input D is sampled in this period. If D is low, node 130 stays high, and output at node 132 either holds low or is pulled low through transistors 116, 118, and 120. If D is high, node 130 is discharged to low through transistors 104, 106, and 108, and output at node 132 holds at high or is pulled high through transistor 114.
Flip-flop 100 has a number of problems. Flip-flop 100 has three transistors 116, 118, and 120 in series which must be activated to discharge a high voltage at node 132 to a low voltage. The more transistors in series, the more time it takes to discharge node 132. This propagation delay is undesirable. Further, flip-flop 100 has a large clock load. Transistors 102, 104, 108, 116, 120, and 126 are all gated to the clock signal CK. This results in increased power consumption over a lighter clock load. Finally, flip-flop 100 has internal node charging and discharging. For example, after the three inverter delay after the clock signal CK switches to a high state, internal node 134 charged to a high state. If data input D is also high, internal node 136 is charged to high. In this case, when the clock switches to low, node 136 starts to discharge. Internal node 134 discharges if D is high. This internal node charging and decharging increases power consumption.
Another prior art flip flop 200 is shown in FIG. 2 and comprises p-type transistor 202 and n-type transistors 204, 206, and 208 connected in series between high potential 210 and ground potential 212, p-type transistor 214 and n-type transistors 216 and 218 connected in series between high potential 210 and ground potential 212, two inverters 220, a NAND gate 222, and latches 224 and 226. Inverters 220 are connected in series between clock signal CK and an input of NAND gate 222. Clock signal CK is also connected to the gates of transistors 202, 208, and 216. Data input D is connected to the gate of transistor 206. A node 228 is defined at the connection between transistors 202 and 204. Node 228 is connected to the gates of transistors 214 and 218, as well as to another input of NAND gate 222 and to latch 224. The output of NAND gate 222 is connected to the gate of transistor 204. Latch 226 is connected to node 230 which is defined between transistors 214 and 216.
The operation of flip-flop 200 is also straightforward. When clock signal CK is at a low state, internal node 228 is precharged to a high voltage, the output from inverters 220 is low, keeping the output of NAND gate 222 high and switching transistor 204 on. Hence, internal node 232 is high. Depending on the data input D, internal node 234 may also be charged high. At the rising edge of clock CK, if D is high, internal nodes 228, 232, and 234 are discharged to pull node 228 to low.
Flip-flop 200 also has a number of problems. Flip-flop 200 has three transistors 204, 206, and 208 in its pull down of node 228. In flip-flop 200, a later signal, the clock signal, is connected to a transistor 208 far from the output. Suppose input D is logic one. When CK is at logic zero, nodes 228, 232, and 234 are all charged. When CK transitions to logic one, nodes 228, 232, and 234 must all be discharged. This discharge of three nodes leads to longer propagation delays and increased energy dissipation.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a flip-flop which has reduced power consumption and increased performance.